CNFET-BASED VLSI LOGICAL EFFORT FRAMEWORK
DOI:
https://doi.org/10.61841/cfh5bv35Keywords:
Carbon nanotube (CNT),, CNT field effect transistor (CNFET), delay, logical effort (LE), and optimization.Abstract
Carbon nanotube discipline-impact transistors (CNFETs) display fantastic ability to build digital systems on advanced generation nodes with big blessings in phrases of electricity, performance, and area (PPA). But, CNFETprecise extra capabilities together with a variety of tubes, pitch, tube position, and diameter in array of tubes play the massive position in correct PPA evaluation. Furthermore, remember and density versions in carbon nanotube (CNTs) due to manufacturing boundaries, just like a presence of steel tubes inside a CNFET channel, degrade a predicted PPA advantages. Furthermore, modeling a CNFET parameters, CNT versions and etching strategies for CNTs create additional complexity during overall performance optimization. As the result, for realistic optimization of CNFET circuit’s performance, it's far vital to comprise an effect of those parameters and versions. In this paper, we suggest put off models for immediate and accurate performance evaluation by using consisting of an effect because of CNFET-precise parameters and CNT versions. For better optimization latest a circuits, we additionally consist of animpact modern day twine parasitic in estimating a postpone today's a man or woman gates. Our optimization device results in a maximum and common postpone development by using 27% and 17%, respectively, and the couple of.5× discount in location for trendy ISCAS and Open SPARC benchmark circuits. Rapid and pretty accurate delay computation in our optimization framework offers notable runtime blessings compared to 497db simulation and statistical-based totally techniques.
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