Design of SRAM Cell and Array Using Adiabatic Logic
DOI:
https://doi.org/10.61841/xhexzy39Keywords:
Differential Cascode, Pre-resolved Adiabatic Logic, VT Variation, Positive-feedback Adiabatic Logic nMOS TechnologyAbstract
A novel SRAM cell together with higher discharge management and increased memory retention competence is planned. At this juncture, the memory array designed for victimization of the planned SRAM unit comprises every part of its word lines. In addition to bit lines obsessed with adiabatically victimization differential cascade and pre resolved adiabatic logic (DCPAL), it also functions like a buffer in the case of the memory group. At this point, the VT disparity will be effectively managed by means of adjusting the ground-line voltage in addition to the power-line voltage of the SRAM cell. Moreover, the styles are enforced victimization 45-nm technology representations in operation at a provide voltage of zero.
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