Classifying 6T SRAM Cell over Processing Voltage and Temperature Curves

Authors

  • Asit Subudhi Department of Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Bhubaneswar Author
  • Saumendra Mohanty Department of Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Bhubaneswar Author

DOI:

https://doi.org/10.61841/m59b3775

Keywords:

Read Delay, SNM Read, Write Delay, leakage power dissipation, 6T SRAM cell and SNM Write.

Abstract

 According to the shifting of centre of mass of the semiconductor firm headed for multimedia, consumer and communications applications, different requirements in term of memory have ascended. The incomparable need for memory being mostly compelled by computer industry. Power consumption is pretty limiting factor for quantity of memory that can be integrated on the single board. This project scrutinizes and classified six transistor SRAM cell over processing temperature and voltage dissimilarities. The parameters of a SRAM being considered are as Read Delay, SNM Read, Write Delay, leakage power dissipation and SNM Write. 

Downloads

Download data is not yet available.

References

[1] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. 2013.

[2] G.-J. Schrijen and V. van der Leest, “Comparative analysis of SRAM memories used as PUF primitives,”

2013.

[3] S. K. Gonugondla, M. Kang, and N. R. Shanbhag, “A7_On-chip training,” IEEE J. Solid-State Circuits, 2018.

[4] J. Yuan and C. Svensson, “High-speed cmos circuit technique,” in High-Performance System Design: Circuits

and Logic, 1999.

[5] S. K. Gonugondla, M. Kang, and N. R. Shanbhag, “A variation-tolerant in-memory machine learning classifier

via on-chip training,” IEEE J. Solid-State Circuits, 2018.

[6] L. Chang et al., “Stable SRAM cell design for the 32 nm node and beyond,” in Digest of Technical Papers -

Symposium on VLSI Technology, 2005

[7] M. E. Sinangil and A. P. Chandrakasan, “An SRAM using output prediction to reduce BL-switching activity

and statistically-gated SA for up to 1.9× reduction in energy/access,” in Digest of Technical Papers - IEEE

International Solid-State Circuits Conference, 2013.

[8] Xuebei Yang and K. Mohanram, “Robust 6T Si tunneling transistor SRAM design,” 2013.

[9] M. E. Sinangil, H. Mair, and A. P. Chandrakasan, “A 28nm high-density 6T SRAM with optimized peripheralassist circuits for operation down to 0.6V,” in Digest of Technical Papers - IEEE International Solid-State

Circuits Conference, 2011.

[10] V. Sharma, M. Gopal, P. Singh, S. K. Vishvakarma, and S. S. Chouhan, “A robust, ultra low-power, datadependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things

applications,” Analog Integr. Circuits Signal Process., 2019.

[11] B. V. V. Satyanarayana and M. Durga Prakash, “Design and Analysis of Heterojunction Tunneling Transistor

(HETT) based Standard 6T SRAM Cell,” Int. J. Eng. Technol., 2018.

[12] A. Nackaerts et al., “A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node

applications using 0.75NA 193nm lithography,” 2005.

Downloads

Published

03.04.2025

How to Cite

Subudhi, A., & Mohanty, S. (2025). Classifying 6T SRAM Cell over Processing Voltage and Temperature Curves. International Journal of Psychosocial Rehabilitation, 23(5), 220-230. https://doi.org/10.61841/m59b3775