Classifying 6T SRAM Cell over Processing Voltage and Temperature Curves
DOI:
https://doi.org/10.61841/m59b3775Keywords:
Read Delay, SNM Read, Write Delay, leakage power dissipation, 6T SRAM cell and SNM Write.Abstract
According to the shifting of centre of mass of the semiconductor firm headed for multimedia, consumer and communications applications, different requirements in term of memory have ascended. The incomparable need for memory being mostly compelled by computer industry. Power consumption is pretty limiting factor for quantity of memory that can be integrated on the single board. This project scrutinizes and classified six transistor SRAM cell over processing temperature and voltage dissimilarities. The parameters of a SRAM being considered are as Read Delay, SNM Read, Write Delay, leakage power dissipation and SNM Write.
Downloads
References
[1] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. 2013.
[2] G.-J. Schrijen and V. van der Leest, “Comparative analysis of SRAM memories used as PUF primitives,”
2013.
[3] S. K. Gonugondla, M. Kang, and N. R. Shanbhag, “A7_On-chip training,” IEEE J. Solid-State Circuits, 2018.
[4] J. Yuan and C. Svensson, “High-speed cmos circuit technique,” in High-Performance System Design: Circuits
and Logic, 1999.
[5] S. K. Gonugondla, M. Kang, and N. R. Shanbhag, “A variation-tolerant in-memory machine learning classifier
via on-chip training,” IEEE J. Solid-State Circuits, 2018.
[6] L. Chang et al., “Stable SRAM cell design for the 32 nm node and beyond,” in Digest of Technical Papers -
Symposium on VLSI Technology, 2005
[7] M. E. Sinangil and A. P. Chandrakasan, “An SRAM using output prediction to reduce BL-switching activity
and statistically-gated SA for up to 1.9× reduction in energy/access,” in Digest of Technical Papers - IEEE
International Solid-State Circuits Conference, 2013.
[8] Xuebei Yang and K. Mohanram, “Robust 6T Si tunneling transistor SRAM design,” 2013.
[9] M. E. Sinangil, H. Mair, and A. P. Chandrakasan, “A 28nm high-density 6T SRAM with optimized peripheralassist circuits for operation down to 0.6V,” in Digest of Technical Papers - IEEE International Solid-State
Circuits Conference, 2011.
[10] V. Sharma, M. Gopal, P. Singh, S. K. Vishvakarma, and S. S. Chouhan, “A robust, ultra low-power, datadependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things
applications,” Analog Integr. Circuits Signal Process., 2019.
[11] B. V. V. Satyanarayana and M. Durga Prakash, “Design and Analysis of Heterojunction Tunneling Transistor
(HETT) based Standard 6T SRAM Cell,” Int. J. Eng. Technol., 2018.
[12] A. Nackaerts et al., “A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node
applications using 0.75NA 193nm lithography,” 2005.
Downloads
Published
Issue
Section
License

This work is licensed under a Creative Commons Attribution 4.0 International License.
You are free to:
- Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
- Adapt — remix, transform, and build upon the material for any purpose, even commercially.
- The licensor cannot revoke these freedoms as long as you follow the license terms.
Under the following terms:
- Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.
Notices:
You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .
No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.