An experimental approach of Power Proficient, High Gain R-2R Ladder DAC and Designed in 90nm CMOS Technology

Authors

  • Hara prasad Tripathy Department of Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Bhubaneswar Author
  • Priyabrata Pattanaik Department of Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Bhubaneswar Author
  • Susanta Kumar Kamilla Department of Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Bhubaneswar Author

DOI:

https://doi.org/10.61841/hx9txe13

Keywords:

DAC, DNL, SNR, SFDR, R-2R ladder, Op-Amp, CMOS, INL, DNL.

Abstract

 In present era of communication system there is a long-felt need for broad band transmission of data (i.e. image, audio or video) at a high rate of data transmission. In this paper an 8 bit D/A converter (DAC) is constructed, simulated in Matlab and compared with the other available DACs. The constructed DAC has very low power consumption of around 2.12 mWatt along with the DNL of 0.40 and INL of 0.78 

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References

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Published

03.04.2025

How to Cite

prasad Tripathy, H., Pattanaik, P., & Kumar Kamilla, S. (2025). An experimental approach of Power Proficient, High Gain R-2R Ladder DAC and Designed in 90nm CMOS Technology. International Journal of Psychosocial Rehabilitation, 23(5), 108-117. https://doi.org/10.61841/hx9txe13