Information Encryption Methods to Reduce Network-on-Chip Energy Efficiency

Authors

  • Dr.D.R.V.A. Sharath Kumar HOD and Professor, Mallareddy Institute of Technology, Hyderabad, India. Author
  • P.A. Lovina Assistant Professor, St. Martin’s Engineering College, Hyderabad, India. Author

DOI:

https://doi.org/10.61841/ebzt8s95

Keywords:

Binary to gray conversion, switching activity, low power, information encoding, interconnection on chip, network on chip (NOC), power investigation, Gray to binary alteration.

Abstract

As innovation shrinks, the energy produced by network-on-chip connections commences to compete among the energy absorbed by certain machinery of the interaction module, notably servers and web switches. In this document, we introduce a collection of information encryption systems directed at decreasing the energy wasted by the NoC connections. Dynamic energy diffusion in connections is a key contributor to NOC energy usage. This attempt uses grey coding systems to analyse the decrease in conversion behavior. Our sophisticated system may not involve any shift in devices or connection design. The prospective system utilizes the signal's binary to color transformation and the recipient's color to binary transformation. An investigational outcome showed the efficiency of the suggested systems in terms of energy dissipation and region distortion in the Web Functionality (WF) relative to information encryption 

Downloads

Download data is not yet available.

References

[1] Nima Jafarzadeh, Maurizio Palesi, Ahmad, and Afzali-Kusha, Data Encoding Techniques for Reducing

Energy Consumption in Network-on-Chip IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., Mar. 2014

[2] W. Wolf, A. A. Jerraya, and G. Martin, “Multiprocessor system-on-chip MPSoC technology,” IEEE Trans.

Comput.-Aided Design Integr. CircuitsSyst., vol. 27, no. 10, pp. 1701–1713, Oct. 2008.

[3] L. Benini and G. De Micheli, “Networks on chips: A new SoC paradigm,” Computer, vol. 35, no. 1, pp. 70–78,

Jan. 2002.

[4] S. E. Lee and N. Bagherzadeh, “A variable frequency link for a power-aware network-on-chip (NoC),” Integr.

VLSI J., vol. 42, no. 4, pp. 479–485, Sep. 2009.

[5] D.Yeh, L. S. Peh, S. Borkar, J. Darringer, A.Agarwal, and W. M. Hwu, “Thousand-core chips

roundtable,” IEEE Design Test Comput., vol. 25, no. 3, pp. 272–278, May–Jun. 2008.

[6] M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz, and V. De,“Formal derivation of optimal active

shielding for low-power on-chip buses,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no.

5, pp. 821–836, May 2006.

[7] R. Ayoub and A. Orailoglu, “A unified transformational approach for reductions in fault vulnerability, power,

and crosstalk noise and delay on processor buses,” in Proc. Design Autom. Conf. Asia South Pacific, vol. 2.

Jan. 2005, pp. 729–734.

[8] M. Palesi, G. Ascia, F. Fazzino, and V. Catania, “Data encoding schemes in networks on chip,” IEEE Trans.

Comput.-Aided Design Integr. Circuits Syst., vol. 30.

[9] L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano, “Asymptotic zero-transition activity encoding

for address busses in low-power microprocessor-based systems,” in Proc. 7th Great Lakes Symp. VLSI, Mar.

1997, pp. 77–82.

[10] E. Musoll, T. Lang, and J. Cortadella, “Working-zone encoding for reducing the energy in microprocessor

address buses,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 568–572, Dec. 1998.

[11] W. Fornaciari, M. Polentarutti, D. Sciuto, and C. Silvano, “Power optimization of system-level address buses

based on software profiling,” in Proc. 8th Int. Workshop Hardw. Softw. Codesign, May 2000, pp. 29–33.

[12] L. Benini, G. De Micheli, E. Macii, M. Poncino, and S. Quer, “Power optimization of core-based systems by

address bus encoding,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 554–562, Dec.

1998.

[13] L. Benini, A. Macii, M. Poncino, and R. Scarsi, “Architectures and synthesis algorithms for power-efficient

bus interfaces,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 9, pp. 969–980, Sep.

2000.

[14] G. Ascia, V. Catania, M. Palesi, and A. Parlato, “Switching activity reduction in embedded systems: A genetic

bus encoding approach,” IEE Proc. Comput. Digit. Tech., vol. 152, no. 6, pp. 756–764, Nov. 2005.

[15] R. Siegmund, C. Kretzschmar, and D. Muller, “Adaptive Partial Businvert encoding for Power-Efficient Data

transfer over wide system buses,” in Proc. 13th Symp. Integr. Circuits Syst. Design, Sep. 2000, pp. 371-376.

[16] S. Youngsoo, C. Soo-Ik, and C. Kiyoung, “Partial bus-invert coding for power optimization of application-specific systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 2, pp. 377–383, Apr. 2001.

[17] M. Palesi, G. Ascia, F. Fazzino, and V. Catania, “Data encoding schemes in networks on chip,” IEEETrans.

Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 5, pp. 774–786, May 2011.

[18] C. G. Lyuh and T. Kim, “Low-power bus encoding with crosstalk delay elimination,” IEE Proc. Comput.

Digit. Tech., vol. 153, no. 2, pp. 93–100, Mar. 2006.

[19] P. P. Pande, H. Zhu, A. Ganguly, and C. Grecu, “Energy reduction through crosstalk avoidance coding in NoC

paradigm,” in Proc. 9th EUROMICRO Conf. Digit. Syst. Design Archit. Methods Tools, Sep. 2006, pp. 689–

695.

[20] K. W. Ki, B. Kwang Hyun, N. Shanbhag, C. L. Liu, and K. M. Sung, “Coupling-driven signal encoding

scheme for low-power interface design,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Nov. 2000,

pp. 318–321.

[21] L. Rung-Bin, “Inter-wire coupling reduction analysis of bus-invert coding,” IEEE Trans. Circuits Syst. I, Reg.

Papers, vol. 55, no. 7, pp. 1911–1920, Aug. 2008.

[22] Z. Khan, T. Arslan, and A. T. Erdogan, “Low power system on chip bus encoding scheme with crosstalk noise

reduction capability,” IEE Proc. Comput. Digit. Tech., vol. 153, no. 2, pp. 101–108, Mar. 2006.

[23] Z. Yan, J. Lach, K. Skadron, and M. R. Stan, “Odd/even bus invert with two-phase transfer for buses with

coupling,” in Proc. Int. Symp. Low Power Electron. Design, 2002, pp. 80–83

Downloads

Published

18.09.2024

How to Cite

Sharath Kumar, D., & Lovina, P. (2024). Information Encryption Methods to Reduce Network-on-Chip Energy Efficiency. International Journal of Psychosocial Rehabilitation, 23(1), 455-465. https://doi.org/10.61841/ebzt8s95